From greeen@iii.org.tw Thu Mar 22 15:06:33 2001 Received: (uucp@localhost) by guadalquivir.fnet.fr (8.8.8/97.02.12/Guadalquivir); id PAA22365; Thu, 22 Mar 2001 15:06:33 +0100 (MET) Received-Date: Thu, 22 Mar 2001 15:06:33 +0100 (MET) Received: from h179-210-243-135.iii.org.tw(210.243.135.179), claiming to be "mta0.iii.org.tw" via SMTP by guadalquivir.fnet.fr, id smtpd022363; Thu Mar 22 15:06:26 2001 Received: from [140.92.66.45] (helo=iiidns.iii.org.tw) by mta0.iii.org.tw with esmtp (Exim 3.16 #1) id 14feQn-000338-00; Wed, 21 Mar 2001 16:57:25 +0800 Received: from Green ([140.92.12.76]) by iiidns.iii.org.tw (8.10.2/8.10.2) with SMTP id f2L8vQt24853; Wed, 21 Mar 2001 16:57:26 +0800 (CST) Message-ID: <000c01c0b1e5$3d278080$4c0c5c8c@trd.iii.org.tw> From: "Greeen-III" To: "LinuxEmbeddedMailList" , "MipsMailList" Subject: r2300_switch.S and traps.c Date: Wed, 21 Mar 2001 16:59:17 +0800 MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_NextPart_000_0009_01C0B228.44284660" X-Priority: 3 X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 5.50.4133.2400 X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4133.2400 This is a multi-part message in MIME format. ------=_NextPart_000_0009_01C0B228.44284660 Content-Type: text/plain; charset="big5" Content-Transfer-Encoding: quoted-printable Hi all, I am in the pthread problem. I guess the reason is context switch. So I trace the code /arch/mips/kernel/traps.c and = /arch/mips/kernel/r2300_switch.S. I have some question want to ask you. 1. What condition the kernel will simulate the instruction "ll" and = "sc"? (In the traps.c) 2. What is the functional of the variable "ll_bit" ? (In the traps.c) 3. What situation does kernel call the resune ? (In the r2300_switch.S) 4. The traps.c is initialize IDT( interrupt descripter table ), Right? = Green ------=_NextPart_000_0009_01C0B228.44284660 Content-Type: text/html; charset="big5" Content-Transfer-Encoding: quoted-printable

Hi all,

I am in the pthread = problem.

I guess the reason is context = switch.

So I trace the code = /arch/mips/kernel/traps.c and=20 /arch/mips/kernel/r2300_switch.S.

I have some question want to = ask you.

1. What condition the kernel = will simulate the instruction=20 "ll" and "sc"? (In the traps.c)

2. What is the functional of = the variable "ll_bit" ? (In the = traps.c)

3. What situation does kernel = call the resune ? (In the=20 r2300_switch.S)

4. The traps.c is initialize = IDT( interrupt descripter=20 table ), Right?

= =20 = =20 = =20 = =20 = =20 = =20 Green

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