# packages

pkgId: 0908d17f95bca1266617287b43e1eb1ee419785ba75998b9dc3abf5c4b2ddbe5
name: coriolis-eda
arch: src
version: 2.5.5
epoch: 0
release: 181.1.355afdc45
summary: Coriolis 2 EDA toolchain
url: https://coriolis.lip6.fr/
rpm_license: BSD-1-Clause AND LGPL-2.0-only AND GPL-2.0-only AND Apache-1.0
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Applications/Engineering
rpm_buildhost: I02-ch2a
rpm_packager: Mazher Iqbal <mazher@lip6.fr>
location_href: src/coriolis-eda-2.5.5-181.1.355afdc45.src.rpm
checksum_type: sha256
description:
  A FOSS EDA tool suite for physical design. Provides an integrated
  place & route for ASICs. Support symbolic layout (Alliance) and
  real layout (GDS). While mainly written in C++, it has an extensive
  Python interface.


pkgId: 03b7a43badf96a4c37ce8416a82637b7a2a393d74ced455947815b4cd93a5ed1
name: coriolis-pdk-ihpsg13g2
arch: src
version: 2024.10.15
epoch: 0
release: 22.1.bfa7190
summary: IHP Open PDK SG13G2
url: https://github.com/IHP-GmbH/IHP-Open-PDK
rpm_license: Apache-2.0
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Productivity/Scientific/Electronics
rpm_buildhost: H02-ch2c
location_href: src/coriolis-pdk-ihpsg13g2-2024.10.15-22.1.bfa7190.src.rpm
checksum_type: sha256
description:
  130nm  BiCMOS Open  Source PDK,  dedicated for  Analog/Digital, Mixed
  Signal and RF Design

  IHP Open  Source PDK project  goal is to  provide a fully  open source
  Process  Design Kit  and related  data, which  can be  used to  create
  manufacturable  designs at  IHP’s facility.   As of  March 2023,  this
  repository is targeting the SG13G2 process node


pkgId: 8902867c8ac6297c2f90c82e7f68089d0298708cbdf7eed8d34e1a21955d69e4
name: tas-yagle
arch: src
version: 3.4.6
epoch: 0
release: 5.1.7c42cd9
summary: Tas/Yagle - Static Timing Analyser
url: https://coriolis.lip6.fr/
rpm_license: GPL-2.0-only
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Applications/Engineering
rpm_buildhost: I04-ch1b
location_href: src/tas-yagle-3.4.6-5.1.7c42cd9.src.rpm
checksum_type: sha256
description:
  STATIC TIMING ANALYSIS
    The  advent   of  semiconductor  fabrication  technologies   now  allows  high
  performance in complex integrated circuits.
    With the increasing complexity of these circuits, static timing analysis (STA)
  has  revealed  itself  as  the  only  feasible  method  ensuring  that  expected
  performances are actually obtained.
    In addition, signal integrity (SI) issues due to crosstalk play a crucial role
  in performance and reliability of these  systems, and must be taken into account
  during the timing analysis.
    However, performance  achievement not  only lies in  fabrication technologies,
  but also  in the way circuits  are designed.  Very high  performance designs are
  obtained with semi or full-custom designs techniques.
    The HITAS platform provides advanced STA and SI solutions at transistor level.
  It has been  built-up in order to allow engineers to  ensure complete timing and
  SI coverage on their digital custom  designs, as well as IP-reuse through timing
  abstraction.
    Furthermore,  hierarchy  handling  through  transparent  timing  views  allows
  full-chip verification, with virtually no limit of capacity in design size.


