# packages

pkgId: 6b99add153ed56262de3e30c635036b2a9fa65551bdeea84e98425a478541109
name: alliance
arch: src
version: 5.0
epoch: 0
release: lp156.111.2
summary: VLSI EDA System
url: http://coriolis.lip6.fr/
rpm_license: GPL-2.0-only
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Applications/Engineering
rpm_buildhost: i04-ch4d
location_href: src/alliance-5.0-lp156.111.2.src.rpm
checksum_type: sha256
description:
  Alliance is a complete set of free CAD tools and portable libraries for
  VLSI design. It includes a VHDL compiler and simulator, logic synthesis
  tools, and automatic place and route tools.

  A complete set of portable CMOS libraries is provided, including a RAM
  generator, a ROM generator and a data-path compiler.

  Alliance is the result of more than ten years effort spent at ASIM department
  of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France).

  Alliance has been used for research projects such as the 875 000 transistors
  StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL
  Router.

  You are kindly requested to mention
  " Designed with alliance (c) LIP6, Sorbonne Université"
  so as to spread the word about "alliance CAD system" and its development team.

  Alliance provides CAD tools covering most of all the digital design flow:

   * VHDL Compilation and Simulation
   * Model checking and formal proof
   * RTL and Logic synthesis
   * Data-Path compilation
   * Macro-cells generation
   * Place and route
   * Layout edition
   * Netlist extraction and verification
   * Design rules checking


pkgId: 821955413f9dd8a880c1a3c01ead7822a86c8f2f60da597378502a46d3eb8519
name: bison
arch: src
version: 3.7.4
epoch: 0
release: lp156.9.1
summary: A GNU general-purpose parser generator
url: http://www.gnu.org/software/bison/
rpm_license: GPLv3+
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Unspecified
rpm_buildhost: h02-ch2a
location_href: src/bison-3.7.4-lp156.9.1.src.rpm
checksum_type: sha256
description:
  Bison is a general purpose parser generator that converts a grammar
  description for an LALR(1) context-free grammar into a C program to
  parse that grammar. Bison can be used to develop a wide range of
  language parsers, from ones used in simple desk calculators to complex
  programming languages. Bison is upwardly compatible with Yacc, so any
  correctly written Yacc grammar should work with Bison without any
  changes. If you know Yacc, you shouldn't have any trouble using
  Bison. You do need to be very proficient in C programming to be able
  to use Bison. Bison is only needed on systems that are used for
  development.

  If your system will be used for C development, you should install
  Bison.


pkgId: b1645199ead38d364317b9fb3c36d023edccd772ea4b9c39feb112a1fea5476f
name: coriolis-eda
arch: src
version: 2.5.5
epoch: 0
release: 193.1.f4c1b74de
summary: Coriolis 2 EDA toolchain
url: https://coriolis.lip6.fr/
rpm_license: BSD-1-Clause AND LGPL-2.0-only AND GPL-2.0-only AND Apache-1.0
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Applications/Engineering
rpm_buildhost: i02-ch1c
rpm_packager: Mazher Iqbal <mazher@lip6.fr>
location_href: src/coriolis-eda-2.5.5-193.1.f4c1b74de.src.rpm
checksum_type: sha256
description:
  A FOSS EDA tool suite for physical design. Provides an integrated
  place & route for ASICs. Support symbolic layout (Alliance) and
  real layout (GDS). While mainly written in C++, it has an extensive
  Python interface.


pkgId: 42f8f28d256b800b909b6825be23c7ca81ba8b4cf6bcf9067b65d8ebb81275a4
name: coriolis-pdk-gf180mcu
arch: src
version: 2025.07.21
epoch: 0
release: 4.15.bfa7190
summary: Global Foundries 180 MCU open PDK
url: https://github.com/google/gf180mcu-pdk.git
rpm_license: Apache-2.0
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Productivity/Scientific/Electronics
rpm_buildhost: i01-ch2d
location_href: src/coriolis-pdk-gf180mcu-2025.07.21-4.15.bfa7190.src.rpm
checksum_type: sha256
description:
  The GF180MCU  open source PDK  is a collaboration between  Google and
  GlobalFoundries to  provide a  fully open  source process  design kit
  (PDK)  and  related  resources  to enable  the  creation  of  designs
  manufacturable at GlobalFoundries's facility  on their 0.18um 3.3V/6V
  MCU process technology.

  The GF180MCU documentation can be found at <https://gf180mcu-pdk.rtfd.io>.


pkgId: a28cf2badefec02067ad0317d3be4829485a666e91612453a2c67dee0253953a
name: coriolis-pdk-ihpsg13g2
arch: src
version: 2024.10.15
epoch: 0
release: 27.10.bfa7190
summary: IHP Open PDK SG13G2
url: https://github.com/IHP-GmbH/IHP-Open-PDK
rpm_license: Apache-2.0
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Productivity/Scientific/Electronics
rpm_buildhost: i02-ch2a
location_href: src/coriolis-pdk-ihpsg13g2-2024.10.15-27.10.bfa7190.src.rpm
checksum_type: sha256
description:
  130nm  BiCMOS Open  Source PDK,  dedicated for  Analog/Digital, Mixed
  Signal and RF Design

  IHP Open  Source PDK project  goal is to  provide a fully  open source
  Process  Design Kit  and related  data, which  can be  used to  create
  manufacturable  designs at  IHP’s facility.   As of  March 2023,  this
  repository is targeting the SG13G2 process node


pkgId: 6e681a04de0a20448ceb24cc17490633cb2ed0cc71555de34a5ac2dcaae1d746
name: ngspice
arch: src
version: 44.2
epoch: 0
release: 1.1
summary: Mixed-level, Mixed-signal Circuit Simulator Based on spice3f5
url: https://ngspice.sourceforge.io
rpm_license: BSD-2-Clause
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Productivity/Scientific/Electronics
rpm_buildhost: i01-ch2b
location_href: src/ngspice-44.2-1.1.src.rpm
checksum_type: sha256
description:
  Ngspice is a mixed-level/mixed-signal circuit simulator. Its code
  is based on three open source software packages: Spice3f5, Cider1b1
  and Xspice.


pkgId: 22851f6cc889eb19b156ab27aec804fc2fa838db88dc60a90686c507b597d245
name: openvaf
arch: src
version: 23.5.0
epoch: 0
release: 5.1
summary: OpenVAF is a Next-Generation Verilog-A compiler
url: https://openvaf.semimod.de/
rpm_license: GPL-3.0-only
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Applications/Engineering
rpm_buildhost: i04-ch2d
location_href: src/openvaf-23.5.0-5.1.src.rpm
checksum_type: sha256
description:
  Circuit simulators play a critical role in the design of electrical circuits.
  Accurate simulations enable circuit designers to validate circuit behavior
  before actual fabrication happens, potentially saving significant re-design
  costs.  The simulation of a circuit critically depends on the so-called compact
  models and therefore:
  * The accuracy of the compact-model equations
  * The quality of the model parameters


pkgId: 0a648624584383f0254fe9826982d551e1b85fd0fe11472874941acb3555be41
name: sv2v
arch: src
version: 0.0.12
epoch: 0
release: 1.1
summary: sv2v - SystemVerilog to Verilog
url: https://github.com/zachjs/sv2v/
rpm_license: BSD-3-Clause
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Applications/Engineering
rpm_buildhost: i03-ch1d
location_href: src/sv2v-0.0.12-1.1.src.rpm
checksum_type: sha256
description:
  sv2v converts SystemVerilog (IEEE 1800-2017) to Verilog (IEEE 1364-2005),
  with an emphasis on supporting synthesizable language constructs.
    The primary goal of this project is to create a completely free and
  open-source tool for converting SystemVerilog to Verilog. While methods
  for performing this conversion already exist, they generally either rely
  on commercial tools, or are limited in scope.
    This project was originally developed to target Yosys, and so allows for
  disabling the conversion of (passing through) those SystemVerilog features
  that Yosys supports.


pkgId: 488e0dc420fba4ddf4d4d1aca13113b6478ed315baeb27f9377cd31abd4af0ce
name: tas-yagle
arch: src
version: 3.4.6
epoch: 0
release: 10.1.ea2ced1
summary: Tas/Yagle - Static Timing Analyser
url: https://coriolis.lip6.fr/
rpm_license: GPL-2.0-only
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Applications/Engineering
rpm_buildhost: i04-ch4d
location_href: src/tas-yagle-3.4.6-10.1.ea2ced1.src.rpm
checksum_type: sha256
description:
  STATIC TIMING ANALYSIS
    The  advent   of  semiconductor  fabrication  technologies   now  allows  high
  performance in complex integrated circuits.
    With the increasing complexity of these circuits, static timing analysis (STA)
  has  revealed  itself  as  the  only  feasible  method  ensuring  that  expected
  performances are actually obtained.
    In addition, signal integrity (SI) issues due to crosstalk play a crucial role
  in performance and reliability of these  systems, and must be taken into account
  during the timing analysis.
    However, performance  achievement not  only lies in  fabrication technologies,
  but also  in the way circuits  are designed.  Very high  performance designs are
  obtained with semi or full-custom designs techniques.
    The HITAS platform provides advanced STA and SI solutions at transistor level.
  It has been  built-up in order to allow engineers to  ensure complete timing and
  SI coverage on their digital custom  designs, as well as IP-reuse through timing
  abstraction.
    Furthermore,  hierarchy  handling  through  transparent  timing  views  allows
  full-chip verification, with virtually no limit of capacity in design size.


pkgId: e9bf873c23fae25f05830e17498ef59c89aa45bb550431a5ccac0344143ae175
name: yosys
arch: src
version: 0.46
epoch: 0
release: 21.11.e97731b9d
summary: Yosys open synthesis suite
url: https://yosyshq.net/yosys/
rpm_license: ISC
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Applications/Engineering
rpm_buildhost: i03-ch1a
location_href: src/yosys-0.46-21.11.e97731b9d.src.rpm
checksum_type: sha256
description:
  This is a framework for RTL synthesis tools. It currently has
  extensive Verilog-2005 support and provides a basic set of
  synthesis algorithms for various application domains.

  Yosys can be adapted to perform any synthesis job by combining
  the existing passes (algorithms) using synthesis scripts and
  adding additional passes as needed by extending the yosys C++
  code base.

  Yosys is free software licensed under the ISC license (a GPL
  compatible license that is similar in terms to the MIT license
  or the 2-clause BSD license).


pkgId: fa482c9ffbe88ad2037b2bded1185c8a09775a22cad8bbaf4e2478e87747f1d3
name: yosys-slang
arch: src
version: 2025.10.31.ba1859e
epoch: 0
release: 16.2
summary: SystemVerilog frontend for Yosys
url: https://github.com/povik/yosys-slang.git
rpm_license: ISC
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Applications/Engineering
rpm_buildhost: i03-ch2c
location_href: src/yosys-slang-2025.10.31.ba1859e-16.2.src.rpm
checksum_type: sha256
description:
  yosys-slang is  a Yosys plugin  providing a new  command (read_slang)
  for loading SystemVerilog designs.
    yosys-slang  builds   on  top  of  the  slang  library  to  provide
  comprehensive   SystemVerilog  support.   The   plugin  supports   an
  (informally defined) synthesizable subset of SystemVerilog in version
  IEEE 1800-2017 or IEEE 1800-2023.


