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Generate a N bits shifter named modelname.
How it works :
if op[0] signal is set to '1' perform a right shift, left shift otherwise.
if op[1] signal is set to '1' perform a sign extention, i.e. an arithmetic shift (only meaningful in case of a right shift).
shamt : specify the shift amount. The wide of this signal (Y) is computed from the operator's wide : Y = log2(N) - 1.
GENLIB_MACRO(DPGEN_SHIFT, "model_shift_32" , F_BEHAV|F_PLACE , 32 ); GENLIB_LOINS( "model_shift_32" , "instance1_shift_32" , "add_sub" , "op[1:0]" , "shamt[4:0]" , "i0[31:0]" , "q[31:0]" , "vdd", "vss", NULL ); |
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